forked from github-mirrors/ale
48 lines
1.6 KiB
VimL
48 lines
1.6 KiB
VimL
" Author: Masahiro H https://github.com/mshr-h
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" Description: verilator for verilog files
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function! ale_linters#verilog#verilator#Handle(buffer, lines)
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" Look for lines like the following.
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"
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" %Error: addr_gen.v:3: syntax error, unexpected IDENTIFIER
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" %Warning-WIDTH: addr_gen.v:26: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS's CONST '20'h0' generates 20 bits.
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" %Warning-UNUSED: test.v:3: Signal is not used: a
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" %Warning-UNDRIVEN: test.v:3: Signal is not driven: clk
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" %Warning-UNUSED: test.v:4: Signal is not used: dout
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" %Warning-BLKSEQ: test.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).
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let l:pattern = '^%\(Warning\|Error\)[^:]*:[^:]\+:\(\d\+\): \(.\+\)$'
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let l:output = []
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for l:line in a:lines
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let l:match = matchlist(l:line, l:pattern)
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if len(l:match) == 0
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continue
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endif
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let l:line = l:match[2] + 0
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let l:type = l:match[1] ==# 'Error' ? 'E' : 'W'
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let l:text = l:match[3]
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call add(l:output, {
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\ 'bufnr': a:buffer,
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\ 'lnum': l:line,
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\ 'vcol': 0,
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\ 'col': 1,
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\ 'text': l:text,
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\ 'type': l:type,
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\ 'nr': -1,
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'verilator',
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\ 'output_stream': 'stderr',
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\ 'executable': 'verilator',
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\ 'command': g:ale#util#stdin_wrapper . ' .v verilator --lint-only -Wall -Wno-DECLFILENAME',
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\ 'callback': 'ale_linters#verilog#verilator#Handle',
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\})
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