forked from github-mirrors/ale
53 lines
1.4 KiB
Plaintext
53 lines
1.4 KiB
Plaintext
Before:
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runtime ale_linters/verilog/verilator.vim
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After:
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call ale#linter#Reset()
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Execute (The verilator handler should parse legacy messages with only line numbers):
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AssertEqual
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\ [
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\ {
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\ 'lnum': 3,
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\ 'type': 'E',
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\ 'text': 'syntax error, unexpected IDENTIFIER',
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\ 'filename': 'foo.v'
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\ },
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\ {
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\ 'lnum': 10,
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\ 'type': 'W',
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\ 'text': 'Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
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\ 'filename': 'bar.v'
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\ },
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\ ],
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\ ale_linters#verilog#verilator#Handle(bufnr(''), [
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\ '%Error: foo.v:3: syntax error, unexpected IDENTIFIER',
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\ '%Warning-BLKSEQ: bar.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
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\ ])
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Execute (The verilator handler should parse new format messages with line and column numbers):
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AssertEqual
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\ [
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\ {
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\ 'lnum': 3,
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\ 'col' : 1,
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\ 'type': 'E',
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\ 'text': 'syntax error, unexpected endmodule, expecting ;',
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\ 'filename': 'bar.v'
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\ },
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\ {
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\ 'lnum': 4,
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\ 'col' : 6,
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\ 'type': 'W',
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\ 'text': 'Signal is not used: r',
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\ 'filename': 'foo.v'
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\ },
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\ ],
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\ ale_linters#verilog#verilator#Handle(bufnr(''), [
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\ '%Error: bar.v:3:1: syntax error, unexpected endmodule, expecting ;',
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\ '%Warning-UNUSED: foo.v:4:6: Signal is not used: r',
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\ ])
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