Add verilator for verilog

This commit is contained in:
mshr-h 2016-10-08 21:38:31 +09:00
parent edc5cedd8c
commit e59264023a
3 changed files with 52 additions and 2 deletions

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@ -47,7 +47,7 @@ name. That seems to be the fairest way to arrange this table.
| SCSS | [sass-lint](https://www.npmjs.com/package/sass-lint), [scss-lint](https://github.com/brigade/scss-lint) |
| Scala | [scalac](http://scala-lang.org) |
| TypeScript | [tslint](https://github.com/palantir/tslint) |
| Verilog | [iverilog](https://github.com/steveicarus/iverilog) |
| Verilog | [iverilog](https://github.com/steveicarus/iverilog), [verilator](http://www.veripool.org/projects/verilator/wiki/Intro) |
| Vim | [vint](https://github.com/Kuniwak/vint) |
| YAML | [yamllint](https://yamllint.readthedocs.io/) |

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@ -0,0 +1,50 @@
if exists('g:loaded_ale_linters_verilog_verilator')
finish
endif
let g:loaded_ale_linters_verilog_verilator = 1
function! ale_linters#verilog#verilator#Handle(buffer, lines)
" Look for lines like the following.
"
" %Error: addr_gen.v:3: syntax error, unexpected IDENTIFIER
" %Warning-WIDTH: addr_gen.v:26: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS's CONST '20'h0' generates 20 bits.
" %Warning-UNUSED: test.v:3: Signal is not used: a
" %Warning-UNDRIVEN: test.v:3: Signal is not driven: clk
" %Warning-UNUSED: test.v:4: Signal is not used: dout
" %Warning-BLKSEQ: test.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).
let pattern = '^%\(Warning\|Error\)[^:]*:[^:]\+:\(\d\+\): \(.\+\)$'
let output = []
for line in a:lines
let l:match = matchlist(line, pattern)
if len(l:match) == 0
continue
endif
let line = l:match[2] + 0
let type = l:match[1] ==# 'Error' ? 'E' : 'W'
let text = l:match[3]
call add(output, {
\ 'bufnr': a:buffer,
\ 'lnum': line,
\ 'vcol': 0,
\ 'col': 1,
\ 'text': text,
\ 'type': type,
\ 'nr': -1,
\})
endfor
return output
endfunction
call ALEAddLinter('verilog', {
\ 'name': 'verilator',
\ 'output_stream': 'stderr',
\ 'executable': 'verilator',
\ 'command': g:ale#util#stdin_wrapper . ' .v verilator --lint-only -Wall -Wno-DECLFILENAME',
\ 'callback': 'ale_linters#verilog#verilator#Handle',
\})

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@ -61,7 +61,7 @@ The following languages and tools are supported.
* SCSS: 'sasslint', 'scsslint'
* Scala: 'scalac'
* TypeScript: 'tslint'
* Verilog: 'iverilog'
* Verilog: 'iverilog', 'verilator'
* Vim: 'vint'
* YAML: 'yamllint'